Verilog Constructs - 2023.2 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID

UG901

Release Date

2023-11-01

Version

2023.2 English

The following table lists the support status of Verilog constructs in Vivado synthesis.

Table 1. Verilog Constructs
Verilog Constants	Support Status
Constant
Integer	Supported
Real	Supported
String	Unsupported
Verilog Data Types
Net types: tri0 tri1 trireg	Unsupported
wand wor	Supported
All Drive strengths	Ignored
Real and realtime registers	Unsupported
All Named events	Unsupported
Delay	Ignored
Verilog Procedural Assignments
assign	Supported with limitations. See Using assign and deassign Statements.
deassign	Supported with limitations. See Using assign and deassign Statements.
force	Unsupported
release	Unsupported
forever statements	Unsupported
repeat statements	Supported, but repeat value must be constant
for statements	Supported, but bounds must be static
delay (#)	Ignored
event (@)	Unsupported
wait	Unsupported
named events	Unsupported
parallel blocks	Unsupported
specify blocks	Ignored
disable	Supported
Verilog Design Hierarchies
module definition	Supported
macromodule definition	Unsupported
hierarchical names	Supported¹
defparam	Supported
array of instances	Supported
configurations	Supported
Verilog Compiler Directives
`celldefine `endcelldefine	Ignored
`default_nettype	Supported
`define	Supported
`ifdef `else `endif	Supported
`undef, `ifndef, `elsif	Supported
`include	Supported
`resetall	Ignored
`timescale	Ignored
`unconnected_drive `nounconnected_drive	Ignored
`uselib	Unsupported
`file, `line	Supported
The processing for hierarchical names is done post-elaboration. Because of this, the connections are not seen in the elaborated view. They only start appearing in the post-synthesis view.