RW_ADDR_COLLISION VHDL Example - RW_ADDR_COLLISION VHDL Example - 2023.2 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)
Document_ID
UG901
Release_Date
2023-11-01
Version
2023.2 English
attribute rw_addr_collision : string;
attribute rw_addr_collision of my_ram : signal is "yes";