KEEP - 2023.2 English

Vivado Design Suite User Guide: Synthesis (UG901)

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2023.2 English

Use the KEEP attribute to prevent optimizations where signals are either optimized or absorbed into logic blocks. This attribute instructs the synthesis tool to keep the signal it was placed on, and that signal is placed in the netlist.

For example, if a signal is an output of a 2-bit AND gate, and it drives another AND gate, the KEEP attribute can be used to prevent that signal from being merged into a larger LUT that encompasses both AND gates.

Be careful when using KEEP with other attributes. In cases where other attributes conflict with KEEP, the attribute usually takes precedence.

KEEP is also commonly used with timing constraints. If there is a timing constraint on a signal that would generally be optimized, KEEP prevents that and allows the correct timing rules to be used.

Note: The KEEP attribute is not supported on the port of a module or entity. If you need to keep specific ports, use the -flatten_hierarchy none setting or put a DONT_TOUCH on the module or entity itself.
Take care when using KEEP attribute on loadless signals. Synthesis keeps those signals resulting in issues later in the flow.

Examples are:

  • When you have a MAX_FANOUT attribute on one signal and a KEEP attribute on a second signal that is driven by the first; the KEEP attribute on the second signal would not allow fanout replication.
  • With a RAM_STYLE="block" , when there is a KEEP on the register that would need to become part of the RAM, the KEEP attribute prevents the block RAM from being inferred.

The supported KEEP values are:

Keeps the signal.
Allows Vivado synthesis to optimize. The FALSE value does not force the tool to remove the signal. The default value is FALSE.

You can place this attribute on any signal, register, or wire.

Note: The KEEP attribute does not force the place and route to keep the signal. Instead, this is accomplished using the DONT_TOUCH attribute.