CASCADE_HEIGHT Verilog example - CASCADE_HEIGHT Verilog example - 2023.2 English

CASCADE_HEIGHT Verilog example - CASCADE_HEIGHT Verilog example - 2023.2 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document_ID

UG901

Release_Date

2023-11-01

Version

2023.2 English

(* cascade_height = 4 *) reg [31:0] ram [(2**15) - 1:0];