Xcelium Simulator Compilation Options - 2023.2 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

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2023.2 English
Table 1. Xcelium Compilation Options
Options Description
Verilog Options Browse to set Verilog include path and to define macro
Generics/Parameters options Specify or browse to set the generic/parameter value
xcelium.compile.tcl.pre Tcl file containing a set of commands that should be invoked before the launch of a compilation
xcelium.compile.v93 Enable VHDL-93 features
xcelium.compile.relax Enable relaxed VHDL interpretation
xcelium.compile.load_glbl Load GLBL module
xcelium.compile.xmvhdl.more_options More XMVHDL compilation options
xcelium.compile.xmvlog.more_options More XMVLOG compilation options
xcelium.compile.xmsc.more_options More XMSC compilation options
xcelium.compile.g++.more_options More G++ compilation options
xcelium.compile.gcc.more_options More GCC compilation options