Vivado Simulator Compilation Options - 2023.2 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

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2023.2 English
Table 1. Vivado Simulator Compilation Options
Option Description
Verilog options Browse to set Verilog include path and to define macro
Generics/Parameters options Specify or browse to set the generic/parameter value
xsim.compile.tcl.pre Tcl file containing set of commands that should be invoked before the launch of compilation
xsim.compile.xvlog.nosort Do not sort Verilog file during compilation
xsim.compile.xvhdl.nosort Do not sort VHDL file during compilation
xsim.compile.xvlog.relax Relax strict Verilog and SystemVerilog language checking rules
xsim.compile.xvhdl.relax Relax strict VHDL language checking rules
xsim.compile.xsc.mt_level Specify the number of sub-compilation jobs to run in parallel
xsim.compile.xvlog.more_options More XVLOG compilation options
xsim.compile.xvhdl.more_options More XVHDL compilation options
xsim.compile.xsc.more_options More XSC compilation options