VCS Simulator Compilation Options - 2023.2 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID
Release Date
2023.2 English
Table 1. VCS Simulator Compilation Options
Option Description
Verilog options Browse to set the Verilog include path and to define macro
Generics/Parameters options Specify or browse to set the generic/parameter values
vcs.compile.tcl.pre a Tcl file containing set of commands that should be invoked before the launch of compilation
vcs.compile.load_glbl Load GLBL module
vcs.compile.vhdlan.more_options More VHDLAN compilation options
vcs.compile.vlogan.more_options Extra VLOGAN compilation options
vcs.compile.syscan.more_options More SYSCAN compilation options
vcs.compile.g++.more_options More G++ compilation options
vcs.compile.gcc.more_options More GCC compilation options