Universal Verification Methodology Support - 2023.2 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

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2023.2 English

AMD Vivado™ integrated design environment supports universal verification methodology (UVM) in Vivado simulator (XSim). The UVM version 1.2 library is precompiled and is available with Vivado. If you are running your design through Vivado, you need not set anything. But if you are running standalone Vivado simulator, you need to pass -L uvm to xvlog and xelab command.

By default, Vivado simulator supports UVM version 1.2. If you want to use the UVM version 1.1, you need to pass -uvm_version 1.1 to xvlog and xelab command. Set the following properties if you use it through the Vivado integrated design environment:

set_property -name {xsim.compile.xvlog.more_options} -value {-uvm_version 1.1} -objects [get_filesets sim_1]
set_property -name {xsim.elaborate.xelab.more_options} -value {-uvm_version 1.1} -objects [get_filesets sim_1]

You can also set these properties from Vivado GUI using Compilation and Elaboration tab in simulation settings. For more information, see Using Simulation Settings.