UNISIM Library - 2023.2 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

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2023.2 English

Functional simulation uses the UNISIM library and contains descriptions for device primitives or lowest-level building blocks.

Important: By default, the compile_simlib command compiles the static simulation files for all the IPs in the IP Catalog.

Encrypted Component Files

The following table lists the UNISIM library component files that let you call precompiled, encrypted library files when you include IP in a design. Include the path that you require in your library search path.

Table 1. Component Files
Component File Description
<Vivado_Install_Dir>/data/verilog/src/unisim_retarget_comp.vp Encrypted Verilog file
<Vivado_Install_Dir>/data/vhdl/src/unisims/unisim_retarget_VCOMP.vhdp Encrypted VHDL file
Important: Verilog module names and file names are uppercase. For example, module BUFG is BUFG.v, and module IBUF is IBUF.v. Ensure that UNISIM primitive instantiations adhere to an uppercase naming convention.


The VHDL UNISIM library is divided into the following files, which specify the primitives for the AMD device families:

  • The component declarations (unisim_VCOMP.vhd)
  • Package files (unisim_VPKG.vhd)

To use these primitives, place the following two lines at the beginning of each file:

library UNISIM;
Important: You must also compile the library and map the library to the simulator. The method depends on the simulator.
Note: For Vivado simulator, the library compilation and mapping is an integrated feature with no further user compilation or mapping required.
Note: Starting in AMD Versalâ„¢ adaptive SoC, AMD is delivering Verilog/SystemVerilog models only for the new primitives. This means that a mixed-language environment is needed for VHDL-only designs, like what has been needed in the past for IPs and XPMs. For more information, see AR76496.

Verilog UNISIM Library

In Verilog, the individual library modules are specified in separate HDL files. This allows the -y library specification switch to search the specified directory for all components and automatically expand the library.

The Verilog UNISIM library cannot be specified in the HDL file prior to using the module. To use the library module, specify the module name using all uppercase letters.

The following example shows the instantiated module name as well as the file name associated with that module:

  • Module BUFG is BUFG.v
  • Module IBUF is IBUF.v

Verilog is case-sensitive. Ensure that UNISIM primitive instantiations adhere to an uppercase naming convention.

If you use precompiled libraries, use the correct simulator command-line switch to point to the precompiled libraries. The following is an example for the Vivado simulator:

-L unisims_ver


-L is the library specification option.