Targeting SystemVerilog for a Specific File - 2023.2 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

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2023.2 English

By default, the Vivado IDE compiles .v files with the Verilog 2001 syntax and .sv files with the SystemVerilog syntax.

To target SystemVerilog for a specific .v file in the Vivado IDE:

  1. Right-click the file and select Set file type as shown in the following figure.

  2. In the Set Type dialog box, shown in the following figure, change the file type from Verilog to SystemVerilog and click OK.

Alternatively, you can use the following command in the Tcl Console:

set_property file_type SystemVerilog [get_files <filename>.v]