Supported Features - 2023.2 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

Document ID
Release Date
2023.2 English

Following are the supported features of VHDL 2008 (IEEE1076-2008):

  • Matching relational operators.
  • Maximum and minimum operators.
  • Shift operators (rol, ror, sll, srl, sla, and sra).
  • Unary logical reduction operators.
  • Mixing array and scalar logical operators.
  • If-else-if and case generate.
  • Sequential assignments.
  • Case? Statements.
  • Select? Statements.
  • Unconstrained element types.
  • boolean_vector and integer_vector array types.
  • Reading output ports.
  • Expressions in port maps.
  • Process (all) statement.
  • Referencing generics in generic lists.
  • Generic types in entities.
  • Relaxed return rules for function return values.
  • Extensions to globally static and locally static expressions.
  • Static ranges and integer expressions in range bounds.
  • Block comments.
  • Context declaration.
  • Array slices in aggregate.
  • Protected types.
  • External name to signal.
  • MOD and REF operators on physical types.
Note: For detailed information about features, see Supported VHDL-2008 Features section in Vivado Design Suite User Guide: Synthesis (UG901).