Supported Data Types - 2023.2 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

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2023.2 English

The following table describes data types allowed on the boundary of C and SystemVerilog, along with mapping of data types from SystemVerilog to C and vice versa.

Table 1. Data Types Allowed on the C-SystemVerilog Boundary
SystemVerilog C Supported Comments
byte char Yes None
shortint short int Yes None
int int Yes None
longint long long Yes None
real double Yes None
shortreal float Yes None
chandle void * Yes None
string const char* Yes None
bit unsigned char Yes sv_0, sv_1
Available on C side using svdpi.h
logic, reg unsigned char Yes sv_0, sv_1, sv_z, sv_x:
Array (packed) of bits svBitVecVal Yes Defined in svdpi.h
Array (packed) of logic/reg svLogicVecVal Yes Defined in svdpi.h
enum Underlying enum type Yes None
Packed struct, union Passed as array Yes None
Unpacked arrays of bit, logic Passed as array Yes C can call SystemVerilog
Unpacked struct Passed as struct Yes None
Unpacked union Passed as struct No None
Open arrays svOpenArrayHandle Yes None

To generate a C header file that provides details on how SystemVerilog data types are mapped to C data types, pass the parameter -dpiheader <file name> to xelab. Additional details on data type mapping are available in the IEEE Standard for SystemVerilog.