String Value Interpretation - 2023.2 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

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2023.2 English

The interpretation of the value string is determined by the declared type of the HDL object and the -radix command line option. The -radix always overrides the default radix determined by the HDL object type.

  • For HDL objects of type logic, the value is a one-dimensional array of the logic type or the value is a string of digits of the specified radix.
    • If the string specifies fewer bits than the type expects, the string is implicitly zero-extended (not sign-extended) to match the length of the type.
    • If the string specifies more bits than the type expects, the extra bits on the MSB side must be zero; otherwise, the command generates a size mismatch error.

    For example, the value 3F specifies eight bits (4 per hex digit) with radix hex and a 6-bit logic array, equivalent to binary 0011 1111. But because the upper two bits of 3 are zero, the value can be assigned to the HDL object. In contrast, the value 7F would generate an error, because the upper two bits are not zero.

    • A scalar (not array or record) logic HDL object has an implicit length of one bit.
    • For a logic array declared as a [left:right] (Verilog) or a(left TO/DOWNTO right), the left-most value bit (after extension/truncation) is assigned to a[left] and the right-most value bit is assigned to a[right].