Skipping Simulation - 2023.2 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

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2023.2 English

To perform a semantic check on the design HDL files, by elaborating and compiling the simulation snapshot without running simulation, you can set the SKIP_SIMULATION property on the simulation fileset:

set_property SKIP_SIMULATION true [get_filesets sim_1]
Important: If you elect to use one of the properties above, disable the Clean up simulation files check box in the simulations settings, or if you are running in batch/Tcl mode, call launch_simulation with -noclean_dir.