Questa Advanced Simulator Compilation Options - 2023.2 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

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2023.2 English
Table 1. Questa Advanced Simulator Compilation Options
Option Description
Verilog options Browse to set Verilog include path and to define macro
Generics/Parameters options Specify or browse to set the generic/parameter value
questasim.compile.tcl.pre Tcl file containing set of commands that should be invoked before the launch of compilation
questasim.compile.vhdl_syntax Specify VHDL syntax
questasim.compile.use_explicit_decl Log all signals
questasim.compile.load_glbl Load GLBL module
questasim.compile.vlog.more_options More VLOG compilation options
questasim.compile.vcom.more_options More VCOM compilation options
questasim.compile.sccom.cores Specify the number of process cores to run in parallel
questasim.compile.sccom.more_options More SCCOM compilation options