Post-Implementation Simulation - 2023.2 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

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2023.2 English

You can perform functional or timing simulation after implementation. Timing simulation is the closest emulation to actually downloading a design to a device. It allows you to ensure that the implemented design meets functional and timing requirements and has the expected behavior in the device.

Important: Performing a thorough timing simulation ensures that the completed design is free of defects that could otherwise be missed, such as:
  • Post-synthesis and post-implementation functionality changes that are caused by:
    • Synthesis properties or constraints that create mismatches (such as full_case and parallel_case)
    • UNISIM properties applied in the Xilinx Design Constraints (XDC) file
    • The interpretation of language during simulation by different simulators
  • Dual port RAM collisions
  • Missing, or improperly applied timing constraints
  • Operation of asynchronous paths
    • Functional issues due to optimization techniques
Note: For Versal devices, post-synthesis, and post-implementation simulation are supported only for fabric logic (PL) and not supported for designs with Hard Blocks (NoC/AIE/PS). Only behavioral simulation is supported for designs utilizing Hard Blocks.