Verilog options |
Browse to set Verilog include path and to define macro |
Generics/Parameters options |
Specify or browse to set the generic/parameter value |
modelsim.compile.tcl.pre |
Tcl file containing a set of commands that should be invoked before the
launch of compilation |
modelsim.compile.vhdl_syntax |
Specify VHDL syntax |
modelsim.compile.use_explicit_decl |
Log all signals |
modelsim.compile.load_glbl |
Load GLBL module |
modelsim.compile.vlog.more_options |
More VLOG compilation options |
modelsim.compile.vcom.more_options |
More VCOM compilation options |