JTAG Simulation - 2023.2 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

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2023.2 English

BSCAN component simulation is supported on all devices.

The simulation supports the interaction of the JTAG ports and some of the JTAG operation commands. The JTAG interface, including an interface to the scan chain, is not fully supported. To simulate this interface:

  1. Instantiate the BSCANE2 component and connect it to the design.
  2. Instantiate the JTAG_SIME2 component into the test bench (not the design).

This becomes:

  • The interface to the external JTAG signals (such as TDI, TDO, and TCK)
  • The communication channel to the BSCAN component

The communication between the components takes place in the VPKG VHDL package file or the glbl Verilog global module. Accordingly, no implicit connections are necessary between the specific JTAG_SIME2 component and the design, or the specific BSCANE2 symbol.

Stimulus can be driven and viewed from the specific JTAG_SIME2 component within the test bench to understand the operation of the JTAG/BSCAN function. Instantiation templates for both of these components are available in both the AMD Vivado™ Design Suite templates and the specific-device libraries guides.