Global Set and Reset and Global 3-State Signals in VHDL - 2023.2 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

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2023.2 English

The GSR and GTS signals are defined in the file: <Vivado_Install_Dir>/data/vhdl/src/unisims/primitive/GLBL_VHD.vhd.

To use the GLBL_VHD component you must instantiate it into the test bench.

The GLBL_VHD component declares the global GSR and GTS signals and automatically pulses GSR for 100 ns.

The following code snippet shows an example of instantiating the GLBL_VHD component in the test bench and changing the assertion pulse width of the Reset on Configuration (ROC) to 90 ns:

GLBL_VHD inst:GLBL_VHD generic map (ROC_WIDTH => 90000);