Generating a Timing Netlist - 2023.2 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

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2023.2 English

You can use a Verilog timing simulation to verify circuit operation after the Vivado tools have calculated the worst-case placed and routed delays.

In many cases, you can use the same test bench that you used for functional simulation to perform a more accurate simulation.

Compare the results from the two simulations to verify that your design is performing as initially specified.

There are two steps to generating a timing simulation netlist:

  1. Generate a simulation netlist file for the design.
  2. Generate an SDF delay file with all the timing delays annotated.
    Important: Vivado IDE supports Verilog timing simulation only.
    Tip: If you are a VHDL user, you can run post-synthesis and post-implementation functional simulation (in which case no standard default format (SDF) annotation is required and the simulation netlist uses the UNISIM library). You can create the netlist using thewrite_vhdl Tcl command. For usage information, see the Vivado Design Suite Tcl Command Reference Guide (UG835).

The following is the Tcl syntax for generating a timing simulation netlist:

write_verilog -mode timesim -sdf_anno true <Verilog_Netlist_Name>