Generating a Netlist - 2023.2 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

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2023.2 English

To run a simulation of a synthesized or implemented design run, the netlist generation process. The netlist generation Tcl commands can take a synthesized or implemented design database and write out a single netlist for the entire design.

The Vivado Design Suite generates a netlist automatically when you launch the simulator using the IDE or the launch_simulation command.

Netlist generation Tcl commands can write SDF and the design netlist. The Vivado Design Suite provides the following Tcl commands:

  • write_verilog: Verilog netlist
  • write_vhdl: VHDL netlist
  • write_sdf: SDF generation
Tip: The SDF values are only estimated during the early design process (for example, during synthesis). As the design process progresses, the accuracy of the timing numbers also progresses as there is more information available in the database.