Enum - 2023.2 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

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2023.2 English

You can define an enumerated type (enum) for conversion to the equivalent SystemVerilog types, svLogicVecVal or svBitVecVal, depending on the base type of enum. For enumerated arrays, equivalent SystemVerilog arrays are created.


SystemVerilog types:
typedef enum reg [3:0] { a = 0, b = 1, c} eType;
eType e;                                         
eType e1[4:3];
typedef enum bit { a = 0, b = 1} eTypeBit;
eTypeBit  e3;
eTypeBit  e4[3:1] ;
C types
svLogicVecVal e[SV_PACKED_DATA_NELEMS(4)];
svLogicVecVal e1[2][SV_PACKED_DATA_NELEMS(4)];
svBit e3;
svBit e4[3];
Tip: The C argument types depend on the base type of the enum and the direction.