Disabling X Propagation for Synchronous Elements - 2023.2 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

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2023.2 English

When a timing violation occurs during a timing simulation, the default behavior of a latch, register, RAM, or other synchronous elements is to output an X to the simulator. This occurs because the actual output value is not known. The output of the register could:

  • Retain its previous value
  • Update to the new value
  • Go metastable, in which a definite value is not settled upon until some time after the clocking of the synchronous element

Because this value cannot be determined, and accurate simulation results cannot be guaranteed, the element outputs an X to represent an unknown value. The X output remains until the next clock cycle in which the next clocked value updates the output if another violation does not occur.

The presence of an X output can significantly affect simulation. For example, an X generated by one register can be propagated to others on subsequent clock cycles. This can cause large portions of the design under test to become unknown.

To correct X-generation:

  • On a synchronous path, analyze the path and fix any timing problems associated with this or other paths to ensure a properly operating circuit.
  • On an asynchronous path, if you cannot otherwise avoid timing violations, disable the X propagation on synchronous elements during timing violations by using the ASYNC_REG property.

When X propagation is disabled, the previous value is retained at the output of the register. In the actual silicon, the register might have changed to the 'new' value. Disabling X propagation might yield simulation results that do not match the silicon behavior.

Exercise care when using this option. Use it only if you cannot otherwise avoid timing violations.