Debugging at the Source Level - 2023.2 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

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2023.2 English

You can debug your HDL source code to track down unexpected behavior in the design. Debugging is accomplished through controlled execution of the source code to determine where issues might be occurring. Available strategies for debugging are:

  • Step through the code line by line: For any design at any point in development, you can use the step command to debug your HDL source code one line at a time to verify that the design is working as expected. After each line of code, run the step command again to continue the analysis. For more information, see Stepping Through a Simulation.
  • Set breakpoints on the specific lines of HDL code, and run the simulation until a breakpoint is reached: In larger designs, it can be cumbersome to stop after each line of HDL source code is run. Breakpoints can be set at any predetermined points in your HDL source code, the simulation is run (either from the beginning of the test bench or from where you currently are in the design) and stops are made at each breakpoint. You can use the Step, Run All, or Run For commands to advance the simulation after a stop. For more information, see the section, Using Breakpoints, below.
  • Set conditions. The tools evaluate each condition and execute Tcl commands when the condition is true. Use the Tcl command:
    add_condition <condition> <instruction>

    See Adding Conditions for more information.