The Compilation tab defines and manages compiler directives, which are stored as properties on the simulation fileset and used by the xvlog and xvhdl utilities to compile Verilog and VHDL source files for simulation.
The Compilation tab defines and manages compiler directives, which are stored as properties on the simulation fileset and used by the xvlog and xvhdl utilities to compile Verilog and VHDL source files for simulation.