Automated Test Bench Generation for Sub-Design - 2023.2 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

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2023.2 English

From 2021.2 onwards, a new methodology is introduced in Vivado simulator (XSim) to create a realistic functional test bench for a language-independent sub-design unit. This methodology currently works for Verilog/VHDL/System Verilog and mixed design of these languages. To use this methodology, two new Tcl commands are introduced. The usage of this new methodology with a real design is explained in subsequent sections.