Analyzing AXI Memory-Mapped (AXI-MM) Interfaces - 2023.2 English

Vivado Design Suite User Guide: Logic Simulation (UG900)

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2023.2 English

This section describes the transaction viewing features specific to AXI4 protocol instances. A protocol instance of an AXI4 interface appears in the wave window with a wave object hierarchy, as shown in the following figure.

Figure 1. AXI-MM Interface

Understanding the Top Summary Row

The top of the wave object hierarchy of an AXI4 protocol instance is the top summary row. This transaction waveform shows the overall read and write activity of an AXI interface based on the following rules:

  • If one or more AXI read transactions are in progress, the top summary shows a Read transaction bar in purple color.
  • If one or more AXI write transactions are in progress, the top summary shows a Write transaction bar in pink color.
  • If one or more of AXI read and write transactions are in progress, the top summary shows Read/Write transaction bar in teal color.

An AXI transaction is an abstract concept not to be confused with the graphical transaction bar. It is a complete data exchange carried out using AXI signaling, including the Address, Data, and optionally Response phases.

Tip: For performance reasons, the wave viewer does not display the transaction bars in different colors when zoomed out. Instead, it displays all transaction bars in teal color. You need to zoom in to distinguish between read and write transactions.

Understanding the Outstanding Reads and Outstanding Writes Rows

There are a group of outstanding AXI read transactions and a group of write transactions located under the top of the wave object hierarchy of an AXI4 protocol instance. An AXI transaction is known as outstanding if the interface master has raised A*VALID or WVALID but the last data phase or optionally response phase has not yet completed. The outstanding reads row shows the current count of outstanding AXI read transactions or is inactive (shown as a thin line) to indicate zero outstanding AXI read transactions. Similarly, the outstanding writes row shows the current count of outstanding AXI write transactions or is inactive to indicate zero outstanding AXI write transactions.

Understanding the Transaction Summary Rows

There is a set of transaction summary rows under each outstanding read and write row labeled as Row <n>, where <n> is an integer. A transaction summary is a transaction bar that depicts a single AXI transaction starting at the first phase and ending at the last phase of an AXI transaction. The assignment of a transaction summary to a specific numbered row conveys no special meaning. Instead, it prevents the overlapping of multiple outstanding AXI transactions in the same row.

Tip: The number of transaction summary rows can increase as simulation progresses. For performance reasons, the wave window updates the rows only when protocol analysis is complete. To see the latest state of the rows during simulation without waiting for the entire simulation to complete, you can pause the simulation and allow the Loading… bars to disappear.

Each transaction summary is labeled with a sequence number. The first AXI transaction has a sequence number of 1, the second AXI transaction has a sequence number of 2, and so on. The progression of sequence numbers for reads and writes are separate from each other and from the AXI transactions of all other protocol instances. For example, a particular protocol instance can have an AXI read transaction with the sequence number 16 and a separate AXI write transaction with the sequence number 16.

Understanding Channel Rows

The channels wave object group is collapsed by default. When you expand the group, you see logic signals for the AXI interface clock and reset (if present) and one transaction row for each AXI channel present in the interface.

Note: Not all five channels are necessarily present in an AXI interface. For read only interfaces, the write channels are absent. For write only interfaces, the read channels are absent. Some AXI interfaces that employ the write channels might omit the response channel if the AXI master has no use of the response information.

Each channel row shows a transaction bar summarizing individual handshakes of that AXI channel from VALID to READY, except that the multiple contiguous data beats of the same AXI transaction appear as a single transaction bar. To visually tie all channel transaction bars of an AXI transaction together, each channel transaction bar is tagged with the same sequence number as the corresponding transaction summary. You can expand the channel row to show key AXI signals for that channel.

Tip: You might need to view protocol instance input signals not included in the wave object hierarchy. While you cannot add the signals to the hierarchy, you can add them before or after the hierarchy.
Tip: The channel transaction bars appear up to one clock cycle after the corresponding AXI signal event. The AXI protocol analyzers consider AXI signal events that occur on or after a positive clock edge to take effect at the following positive clock edge.

When you hover over any channel transaction bar, association, or transaction summary using your mouse, a tooltip appears showing the values of the informational AXI address channel signals from the address phase of the AXI transaction.

Note: Optional AXI address channel signals that are absent from the interface are omitted from the tooltip.

When you select a channel transaction bar, associations appear for all channel transaction bars participating in the same AXI transaction as the selected transaction bar. You can click the tails of the association arrows to follow the progress of the AXI transaction from address phase through response phase. The chain of associations always begins with the address phase transaction even if the data phase precedes the address phase.

Error Conditions

If there is a handshaking error on the interface, you might see a sequence number on a channel transaction consisting of a string of all 9s. This sequence number indicates that the data and/or response phases could not be matched with an address and/or data phase. Common causes are mismatched read/write ID tags and the protocol analyzer being held in reset (ARESET or ARESETn signal active) while the AXI phases are in progress.

Because certain configurations of an AXI interconnect are optimized for performance rather than transaction debugging, AXI interfaces internal to an AXI interconnect might respect a different reset signal than the one connected to the interface causing transaction errors in the wave viewer. If you observe transaction errors on the interface, it is recommended that you monitor interfaces on the outside of the interconnect instead.