UltraScale Architecture Memory IP I/O Planning in the Vivado IDE - 2023.2 English

Vivado Design Suite User Guide: I/O and Clock Planning (UG899)

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2023.2 English

If your design contains UltraScale architecture Memory IP, the Vivado IDE includes the following special features:

  • Groups I/O ports for each Memory IP into port interfaces in the I/O Ports window, which enables group selection and modification
  • Prevents all Memory IP-related ports from using the interactive port placement features, such as drag and drop, swap ports, or manual moving of ports in the graphical views
  • Provides the Memory Bank/Byte Planner, which allows automatic or manual assignment of memory I/O pin groups to I/O banks and byte lanes

You can perform interactive I/O planning by opening either the elaborated RTL design or the synthesized design in the Vivado IDE. For both elaborated and synthesized designs, you can use the same basic process and commands. However, the Vivado tools perform more detailed DRCs in the synthesized design.