Interfacing with the PCB Design - 2023.2 English - UG899

Vivado Design Suite User Guide: I/O and Clock Planning (UG899)
Document ID
UG899
Release Date
2023-10-18
Version
2023.2 English
The Vivado pin planner provides an effective way to select the pin assignments for the design. Choosing correct resources enables a faster and cleaner design process. The recommendations in this section help prevent board layout, pin assignment, and FPGA resource conflict. For more information on PCB and pin planning, see one of the following guides for your device:
  • 7 Series FPGAs PCB Design Guide (UG483)
  • UltraScale Architecture PCB Design User Guide (UG583)
  • Zynq-7000 SoC PCB Design Guide (UG933)