Working with Debug IP - 2023.2 English

Vivado Design Suite User Guide: Designing with IP (UG896)

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2023.2 English

The Vivado Design Suite includes features to let you perform in-system programming and debugging of the post-implemented design in a device. The benefits of debugging your design in-system include debugging your timing-accurate, post-implemented design in the actual system environment running at system speeds.

You can use the Vivado Lab Edition tools to test and verify the IP capabilities when attached to an AMD board with a JTAG connection. The available debug IP cores include:

  • Vivado Integrated Logic Analyzer: The integrated logic analyzer (ILA) also called Vivado logic analyzer, lets you perform in-system debugging of post-implemented designs on an FPGA.

    Use this feature when you need to monitor signals in a design. You can also use this feature to trigger on hardware events and capture data at system speeds. You can instantiate the ILA core in your RTL code or insert the core, post-synthesis, in the Vivado design flow.

  • Vivado Virtual I/O Analyzer: The virtual input/output (VIO) debug feature, also called the Vivado serial I/O analyzer can both monitor and drive internal FPGA signals in real time. In the absence of physical access to the target hardware, you can use this debug feature to drive and monitor signals that are present on the real hardware.

    This debug core must be instantiated in the RTL code; consequently, you need to know what nets to drive.

  • IBERT Serial Analyzer: The integrated bit error ratio tester (IBERT) serial analyzer enables in-system serial I/O validation and debug. This allows you to measure and optimize your high-speed serial I/O links in your FPGA-based system.

    Use the LogiCORE IBERT Serial Analyzer when you are interested in addressing a range of in-system debug and validation problems from simple clocking and connectivity issues to complex margin analysis and channel optimization issues.

    Using this core you can measure the quality of a signal after a receiver equalization is applied to the received signal. This ensures that you are measuring at the optimal point in the TX-to-RX channel and thereby real and accurate data.

    An example design can be generated for any customization of the IBERT core. After you have customized and generated a core instance, right-click the generated core and select Open IP Example Design feature for this core.

  • JTAG to AXI: The JTAG-to-AXI debug feature generates AXI transactions that interact with various AXI4 and AXI4-Lite slave cores in a system that is running in hardware.

    Use this core to generate AXI transactions and debug and to drive AXI signals internal to an FPGA at run time. You can use this core in IP designs without processors as well. The IP catalog lists the core under the Debug category.

    See the following documents for more information:

    • IBERT 7 Series GTX Transceivers LogiCORE IP Product Guide (PG132)
    • IBERT 7 Series GTP Transceivers LogiCORE IP Product Guide (PG133)
    • IBERT 7 Series GTH Transceivers LogiCORE IP Product Guide (PG152)
    • Integrated Logic Analyzer LogiCORE IP Product Guide (PG172)
    • JTag to AXI LogiCORE IP Product Guide (UG174)
    • Vivado Design Suite User Guide: Programming and Debugging (UG908)
    • Vivado Design Suite Tutorial: Programming and Debugging (UG936)
    • UltraFast Design Methodology Guide for the Vivado Design Suite (UG949)