Third-Party Synthesis Flow - 2023.2 English

Vivado Design Suite User Guide: Designing with IP (UG896)

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2023.2 English

When using a Synopsys Synplify Pro or Mentor Graphics Precision netlist for synthesis of a design that has AMD IP, the recommended flow is to use the Manage IP flow to create and customize IP (including AMD XPMs), and generate output products for the IP including the synthesis design checkpoint (DCP) for each IP.

When you generate the DCP file, stub files are created to infer a black box when used with the third-party synthesis tool: <ip_name>_stub.v and <ip_name>_stub.vhdl.

Add the Verilog or the VHDL stub file to the project for use by the third-party synthesis tool. The Verilog or VHDL stub file infers a black box during synthesis and also prevents the synthesis tool from adding I/O buffers.

The <ip_name>_stub.v and the <ip_name>_stub.vhdl contain synthesis directives that prevent the third-party synthesis tool from inferring I/O buffers for the IP if the IP connects to top-level ports. You can change these directives as required for use with third-party synthesis tools.

Generate a netlist for your top-level design with the third-party synthesis tool.

Note: See the AMD Vivado™ Design Suite User Guide: System-Level Design Entry (UG895) for more information about netlist projects.

Create a Vivado netlist project to place and route the top-level design, and generate the bitstream for the device.

You can also create an RTL project for the design, and encapsulate the EDIF netlist from the third-party synthesis tool in a wrapper, and implement the design with the following steps:

  1. Create an HDL wrapper around the EDIF netlist produced by the third-party synthesis tool.
  2. Select the hierarchy tab of the sources window.
  3. Right-click and select Hierarchy Update, and check the No Update, Manual Compile Order option.
  4. Add the following into the AMD Vivado™ netlist project:
    • The netlist from the third-party synthesis tool
    • User-level, top-level design constraints
    • The XCI files for the IP (one XCI file per IP)

    The netlist in the IP DCP and the XDC output products are used automatically during implementation when using the XCI file for the IP.

  5. Implement the design.

    Vivado implementation adds any required I/O buffers if they are not already present in the DCP of the IP.

    Use the IP XCI file when referencing AMD IP in either Project Mode or Non-Project Mode and not the DCP file directly. While the DCP does contain constraints, they are resolved Out-Of-Context of the end-user constraints. Using the XCI results in the XDC output product for the IP being applied after all the netlists are combined (end-user and IP). Additionally, any Tcl script in the IP XDC is evaluated in context of the end-user constraints and netlist.

Example Tcl Script for Third-Party Synthesis in Non-Project Mode

# Set target part 
set_part <part>
# Read the netlist from third-party synthesis tool
read_edif top.edif 
# Read in the IP XCIs
read_ip ip1.xci
read_ip ip2.xci
# read in top level constraints
read_xdc top.xdc
# Implement the design
link_design -top <top> 
write_bitstream -file <name>
Note: Ensure that, when reading in the IP, you are reading the XCI file from the location where the output products of the IP were previously generated or alternatively, read in the XCI file and generate the IP using the synth_ip command.

Example Tcl Script for Third-Party Synthesis in Project Mode

# Create a project on disk 
create_project <name> -part <part>
# configure as a netlist project
set_property design_mode "GateLvl" [current_fileset]
set_property top <top> [current_fileset]
# Add in the netlist from third-party synthesis tool
add_files top.edif
# Add in XCI files for the IP
add_files {ip1.xci ip2.xci ip3.xci}
# Add in top level constraints: this might include XDC files from the third-party 
# synthesis tool
add_files top.xdc
# Launch implementation
launch_run impl_1 -to write_bitstream