Working with IP and IP Subsystems - 2023.2 English

Vivado Design Suite User Guide: Design Flows Overview (UG892)

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2023.2 English

In Non-Project Mode, output products must be generated for the IP or block designs prior to launching the top-level synthesis. You can configure IP to use RTL sources and constraints, or use the OOC netlist from a synthesized design checkpoint as the source in the top-level design. The default behavior is to generate an OOC design checkpoint for each IP.

In Non-Project Mode, you can add IP to your design using any of the following methods:

  • IP generated using the Vivado IP catalog (.xci format or .xcix format for core container)

    If the out-of-context design checkpoint file exists in the IP directory, it is used for implementation and a black box is inserted for synthesis. If a design checkpoint file does not exist in the IP directory, the RTL and constraints sources are used for global synthesis and implementation.

  • Use Tcl commands to configure and generate the IP or block design.

    Using Tcl ensures that the IP is configured, generated, and synthesized with each run.

Important: When using IP in Project Mode or Non-Project Mode, always use the XCI file not the DCP file. This ensures that IP output products are used consistently during all stages of the design flow. If the IP was synthesized out-of-context and already has an associated DCP file, the DCP file is automatically used and the IP is not re-synthesized. For more information, see the Vivado Design Suite User Guide: Designing with IP (UG896).

For more information, see the Vivado Design Suite User Guide: Designing with IP (UG896) and the Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994).