Validating IP Subsystems - 2023.2 English

Vivado Design Suite User Guide: Design Flows Overview (UG892)

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2023.2 English

IP integrator runs basic design rule checks in real time as the design is being assembled. However, there is still a potential for design errors, such as the frequency on a clock pin can be set incorrectly. The tool can catch these types of errors by running a more thorough design validation. You can run design validation by selecting Tools > Validate Design or through the Tcl command validate_bd_design.

The Validate Design command applies design rule checks on the block design and reports warnings and/or errors found in the design. You can cross-probe the warnings and/or errors from the Messages window to locate objects in the block diagram. AMD recommends validating a block design to catch errors that would otherwise be found later in the design flow.

Running design validation also runs Parameter Propagation on the block design. Parameter Propagation enables IP integrator to automatically update the parameters associated with a given IP based on its context and its connections in the design. You can package custom IP with specific parameter propagation rules, and IP integrator applies these rules as the block diagram is generated and validated. See the Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994) for more information.