Using Memory IP - 2023.2 English

Vivado Design Suite User Guide: Design Flows Overview (UG892)

Document ID
UG892
Release Date
2023-10-18
Version
2023.2 English

Additional I/O pin planning steps are required when using AMD memory IP. After the IP is customized, you then assign the top-level I/O ports to physical package pins in either the elaborated or synthesized design in the Vivado IDE.

All of the ports associated with each memory IP are grouped together into an I/O Port Interface for easier identification and assignment. A Memory Bank/Byte Planner is provided to assist you with assigning Memory I/O pin groups to Byte lanes on the physical device pins. For more information, see the Vivado Design Suite User Guide: I/O and Clock Planning (UG899).

If you have memory IP in your design, see the following resources:

  • For details on simulation, see the UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide (PG150).
  • For an example of simulating memory IP with a MicroBlazeā„¢ processor design, see the Reference System: Kintex 7 MicroBlaze System Simulation Using IP Integrator (XAPP1180).