Referencing RTL Modules in Block Designs - 2023.2 English

Vivado Design Suite User Guide: Design Flows Overview (UG892)

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2023.2 English

The Module Reference feature of the Vivado IP integrator lets you quickly add a module or entity definition from a Verilog or VHDL source file directly into your block design. This provides a means of quickly adding RTL modules without having to go through the process of packaging the RTL as an IP to be added through the Vivado IP catalog. The Module Reference flow is quick but does not offer the benefits of working through the IP catalog. Both flows have benefits and associated limitations. Refer to the Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994) for more information.