Logic Synthesis - 2023.2 English

Vivado Design Suite User Guide: Design Flows Overview (UG892)

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2023.2 English

Vivado synthesis enables you to configure, launch, and monitor synthesis runs. The Vivado IDE displays the synthesis results and creates report files. You can select synthesis warnings and errors from the Messages window to highlight the logic in the RTL source files.

You can launch multiple synthesis runs concurrently or serially. On a Linux system, you can launch runs locally or on remote servers. With multiple synthesis runs, Vivado synthesis creates multiple netlists that are stored with the Vivado Design Suite project. You can open different versions of the synthesized netlist in the Vivado IDE to perform device and design analysis. You can also create constraints for I/O pin planning, timing, floorplanning, and implementation. The most comprehensive list of DRCs is available after a synthesized netlist is produced, when clock and clock logic are available for analysis and placement.

For more information, see the Vivado Design Suite User Guide: Synthesis (UG901).
Note: Launching multiple jobs simultaneously on the same machine can exhaust memory, resulting in random Vivado crashes. Ensure to reserve enough memory for all jobs running on a single machine.