IP Constraints - 2023.2 English

Vivado Design Suite User Guide: Design Flows Overview (UG892)

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2023.2 English

Many IP cores contain XDC constraint files that are used during Vivado synthesis and implementation. These constraints are applied automatically in both Project Mode and Non-Project Mode if the IP is customized from the Vivado IP catalog.

Many IP cores reference their input clocks in these XDC files. These clocks can come either from the user through the top level design, or from other IP cores in the design. By default, the Vivado tools process any IP clock creation and any user-defined top-level clock creation early. This process makes these clocks available to the IP cores that require them. Refer to Vivado Design Suite User Guide: Designing with IP (UG896) for more information.