write_verilog - 2023.2 English

Vivado Design Suite Tcl Command Reference Guide (UG835)

Document ID
Release Date
2023.2 English

Export the current netlist in Verilog format


write_verilog [‑cell <arg>] [‑mode <arg>] [‑lib] [‑port_diff_buffers]
    [‑write_all_overrides] [‑keep_vcc_gnd] [‑rename_top <arg>]
    [‑sdf_anno <arg>] [‑sdf_file <arg>] [‑force] [‑include_xilinx_libs]
    [‑logic_function_stripped] [‑skip_clock_attributes] [‑quiet] [‑verbose]


The name of the output file or directory.


Name Description
[-cell] Root of the design to write, e.g. des.subblk.cpu Default: whole design
[-mode] Values: design, pin_planning, synth_stub, sta, funcsim, timesim Default: design
[-lib] Write each library into a separate file
[-port_diff_buffers] Output differential buffers when writing in -port mode
[-write_all_overrides] Write parameter overrides on Xilinx primitives even if the override value is the same as the default value
[-keep_vcc_gnd] Don't replace VCC/GND instances by literal constants on load terminals. For simulation modes only.
[-rename_top] Replace top module name with custom name e.g. netlist Default: new top module name
[-sdf_anno] Specify if sdf_annotate system task statement is generated
[-sdf_file] Full path to sdf file location Default: <file>.sdf
[-force] Overwrite existing file
[-include_xilinx_libs] Include simulation models directly in netlist instead of linking to library
[-logic_function_stripped] Convert INIT strings on LUTs & RAMBs to fixed values. Resulting netlist will not behave correctly.
[-skip_clock_attributes] Do not write the default special clock signal attributes when writing the synthesis directive in synth_stub mode.
[-quiet] Ignore command errors
[-verbose] Suspend message limits during command execution
<file> Which file to write




Write a Verilog netlist of the current design or from a specific cell of the design to the specified file or directory. The output is a IEEE 1364-2001 compliant Verilog HDL file that contains netlist information obtained from the input design files.

You can output a complete netlist of the design or specific cell, or output a port list for the design, or a Verilog netlist for simulation or static timing analysis.


-cell <arg> - (Optional) Write the Verilog netlist from a specified cell or block level of the design hierarchy. The output Verilog file or files will only include information contained within the specified cell or module.

-mode <arg> - (Optional) The mode to use when writing the Verilog file. By default, the Verilog netlist is written for the whole design. Valid mode values are:

  • design - Output a Verilog netlist for the whole design. This acts as a snapshot of the design, including all post placement, implementation, and routing information in the netlist.
  • pin_planning - Output only the I/O ports for the top-level of the design.
  • synth_stub - Output the ports from the top-level of the design for use as a synthesis stub.
  • sta - Output a Verilog netlist to be used for static timing analysis (STA).
  • funcsim - Output a Verilog netlist to be used for functional simulation. The output netlist is not suitable for synthesis.
  • timesim - Output a Verilog netlist to be used for timing simulation. The output netlist is not suitable for synthesis.

-lib - (Optional) Create a separate Verilog file for each library used by the design.

Note: The -library option can only be used for simulation. Vivado™ synthesis will treat all Verilog files as being in the default work library.

-port_diff_buffers - (Optional) Add the differential pair buffers and internal wires associated with those buffers into the output ports list. This argument is only valid when -mode pin_planning or -mode synth_stub is specified.

-write_all_overrides [ true | false ] - (Optional) Write parameter overrides, in the design to the Verilog output even if the value of the parameter is the same as the defined primitive default value. If the option is false then parameter values which are equivalent to the primitive defaults are not output to the Verilog file. Setting this option to true will not change the result but makes the output Verilog more verbose.

-keep_vcc_gnd - (Optional) By default, when writing a nelist for simulation, or from an IP integrator block design, the Vivado Design Suite replaces VCC and GND primitives, and the nets they drive, with literal constants on each of the loads on the net. The -keep_vcc_gnd option disables this default behavior and preserves the VCC or GND primitives.

-rename_top <arg> - (Optional) Rename the top module in the output as specified. This option only works with -mode funcsim or -mode timesim to allow the Verilog netlist to plug into top-level simulation test benches.

-sdf_anno [ true | false ] - (Optional) Add the $sdf_annotate statement to the Verilog netlist. Valid values are true (or 1) and false (or 0). This option only works with -mode timesim, and is set to false by default.

-sdf_file <arg> - (Optional) The path and filename of the SDF file to use when writing the $sdf_annotate statement into the output Verilog file. When not specified, the SDF file is assumed to have the same name and path as the Verilog output specified by <file>, with a file extension of .sdf. The SDF file must be separately written to the specified file path and name using the write_sdf command.

-force - (Optional) Overwrite the Verilog files if they already exists.

-include_xilinx_libs - (Optional) Write the simulation models directly in the output netlist file rather than pointing to the libraries by reference.

-logic_function_stripped - (Optional) Hides the INIT values for LUTs & RAMs by converting them to fixed values in order to create a netlist for debug purposes that will not behave properly in simulation or synthesis.

-skip_clock_attributes - By default under synth_stub mode, module terminals connected to clock are marked as such with a special synthesis directive for clock signals. With this option, the synthesis directive for clock signals is omitted and they are treated as regular terminals.

-quiet - (Optional) Execute the command quietly, returning no messages from the command. The command also returns TCL_OK regardless of any errors encountered during execution.
Note: Any errors encountered on the command-line, while launching the command, will be returned. Only errors occurring inside the command will be trapped.
-verbose - (Optional) Temporarily override any message limits and return all messages from this command.
Note: Message limits can be defined with the set_msg_config command.

<file> - (Required) The path and filename of the Verilog file to write. The path is optional, but if one is not provided the Verilog file will be written to the current working directory, or the directory from which the Vivado tool was launched.


The following example writes a Verilog simulation netlist file for the whole design to the specified file and path:

write_verilog C:/Data/my_verilog.v

In the following example, because the -mode timesim and -sdf_anno options are specified, the $sdf_annotate statement will be added to the Verilog netlist. However, since the -sdf_file option is not specified, the SDF file is assumed to have the same name as the Verilog output file, with an .sdf file extension:

write_verilog C:/Data/my_verilog.net -mode timesim -sdf_anno true
Note: The SDF filename written to the $sdf_annotate statement will be my_verilog.sdf.

In the following example, the functional simulation mode is specified, the option to keep VCC and GND primitives in the output simulation netlist is enabled, and the output file is specified:

write_verilog -mode funcsim -keep_vcc_gnd out.v