set_value - 2023.2 English

Vivado Design Suite Tcl Command Reference Guide (UG835)

Document ID
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2023.2 English

Set the current value of an HDL object (variable, signal, wire, or reg) to a specified value


set_value [‑radix <arg>] [‑quiet] [‑verbose] <hdl_object> <value>


Name Description
[-radix] radix specifies the radix to use for interpreting value. Allowed values are: default, dec, bin, oct, hex, unsigned, ascii, smag
[-quiet] Ignore command errors
[-verbose] Suspend message limits during command execution
<hdl_object> Set the value on the given hdl_object.
<value> The value to assign to the specified object.



Specify the value of a single HDL object at the current simulation run time.

HDL objects include HDL signals, variables, or constants as defined in the Verilog or VHDL test bench and source files. An HDL signal includes Verilog wire or reg entities, and VHDL signals. Examples of HDL variables include Verilog real, realtime, time, and event.

HDL constants include Verilog parameters and localparams, and VHDL generic and constants. The HDL scope, or scope, is defined by a declarative region in the HDL code such as a module, function, task, process, or begin-end blocks in Verilog. VHDL scopes include entity/architecture definitions, block, function, procedure, and process blocks.


-radix <arg> - (Optional) Specifies the radix to use when returning the value of the specified object. Allowed values are: default, dec, bin, oct, hex, unsigned, ascii, or smag.

Note: The radix dec indicates a signed decimal. Specify the radix unsigned when dealing with unsigned data.
-quiet - (Optional) Execute the command quietly, returning no messages from the command. The command also returns TCL_OK regardless of any errors encountered during execution.
Note: Any errors encountered on the command-line, while launching the command, will be returned. Only errors occurring inside the command will be trapped.
-verbose - (Optional) Temporarily override any message limits and return all messages from this command.
Note: Message limits can be defined with the set_msg_config command.

<hdl_object> - (Required) Specifies a single HDL object to get the value of. The object can be specified by name, or can be returned as an object from the get_objects command.

<value> - (Required) The value to set the specified object to. The specified <value> depends on the type of the <hdl_object>. HDL object types include: "logic", floating point, VHDL enumerated, and VHDL integral. For all but "logic" the -radix option is ignored.

  • "Logic" does not refer to an actual HDL object type, but means any object whose values are similar to those of VHDL std_logic, such as:
    • the Verilog implicit 4-state bit type,
    • the VHDL bit and std_logic predefined types,
    • any VHDL enumeration type which is a subset of std_logic, including the character literals '0' and '1'.
  • For logic types the value depends on the radix:
    • If the specified value has fewer bits than the logic type expects, the value is zero extended, but not sign extended, to match the expected length.
    • If the specified value has more bits than the logic type expects, the extra bits on the MSB side should all be zeros, or the Vivado™ simulator will return a "size mismatch" error.
  • Accepted values for floating point objects are floating point values.
  • The accepted value for non-logic VHDL enumerated types is a scalar value from the enumerated set of values, without single quotes in the case of characters.
  • Accepted values for VHDL integral types is a signed decimal integer in the range accepted by the type.


The following example sets the value of the sysClk signal:

set_value sysClk Z

This example uses the bin, dec, and unsigned radix to specify the same value on the given bus:

set_value -radix bin /test/bench_VStatus_pad_0_i[7:0] 10100101
set_value -radix unsigned /test/bench_VStatus_pad_0_i[7:0] 165
set_value -radix dec /test/bench_VStatus_pad_0_i[7:0] -91

The following example shows the bit extension performed when the provided value has fewer bits than the logic type expects:

set_value -radix bin /test/bench_VStatus_pad_0_i[7:0] 101
get_value -radix bin /test/bench_VStatus_pad_0_i[7:0]

The following example shows the bit truncation performed when the provided value has more bits than the logic type expects:

set_value -radix bin /test/bench_VStatus_pad_0_i[7:0] 0010100101
get_value -radix bin /test/bench_VStatus_pad_0_i[7:0]
set_value -radix bin /test/bench_VStatus_pad_0_i[7:0] 1110100101
ERROR: [#UNDEF] Object size 8 does not match size of given value 1110100101
Note: In the second set_value command, the extra bits are not zero, and so an error is returned.