rename a cell
Syntax
rename_cell ‑to <arg> [‑quiet] [‑verbose] <cell>...Usage
| Name | Description |
|---|---|
-to
|
New name |
[-quiet]
|
Ignore command errors |
[-verbose]
|
Suspend message limits during command execution |
<cell>
|
Cell to rename |
Categories
Description
Rename a single hierarchical or leaf-level cell in the current synthesized or implemented design.
write_checkpoint command, or may be exported to a netlist file such as Verilog, VHDL, or EDIF, using the appropriate write_* command.
Changes to the names of cells, nets, pins, and ports, will also affect the design constraints defined in the in-memory design. Constraints are automatically modified to target the new object name, however these are not written back to the source XDC file. Saving the modified in-memory design using write_checkpoint will save both the renamed objects and modified constraints.
This command returns nothing if successful, or an error if it fails.
Arguments
-to <arg> - (Required) Specify the new name to assign to the specified cell. Specified names can not contain Tcl special characters: '"\{};$#
-quiet - (Optional) Execute the command quietly, returning no messages from the command. The command also returns TCL_OK regardless of any errors encountered during execution.
-verbose - (Optional) Temporarily override any message limits and return all messages from this command.
set_msg_config command.
<cell> - (Required) Instance name of the cell to rename.
Examples
The following example changes the name of the hierarchical or1200_cpu cell as specified:
rename_cell -to or1200_gpu or1200_cpu