remove_forces - 2023.2 English

Vivado Design Suite Tcl Command Reference Guide (UG835)

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2023.2 English

Release force on signal, wire, or reg applied using 'add_force' command


remove_forces [‑all] [‑quiet] [‑verbose] [<ForceObj>...]


Name Description
[-all] Remove all forces
[-quiet] Ignore command errors
[-verbose] Suspend message limits during command execution
[<ForceObj>] ForceObj or id's



Remove the specified force objects, or force IDs from the current simulation.

Forces are applied to specific HDL objects using the add_forces command. This command removes those forces from the current simulation.

Important: If there are force/release statements on an HDL object in the test bench or module, these statements are overridden by the add_force command. When the remove_force command releases these objects to resume their normal operation, the Verilog force/release statements resume their effect.

This command returns nothing if successful, or returns an error if it fails.


-all - (Optional) Remove all forces from the current simulation.

-quiet - (Optional) Execute the command quietly, returning no messages from the command. The command also returns TCL_OK regardless of any errors encountered during execution.
Note: Any errors encountered on the command-line, while launching the command, will be returned. Only errors occurring inside the command will be trapped.
-verbose - (Optional) Temporarily override any message limits and return all messages from this command.
Note: Message limits can be defined with the set_msg_config command.

<ForceObj> - (Optional) Remove only the specified force object or objects. The force ID is returned by the add_force command when the force is created.


The following example creates a force object using the add_force command, and captures the force ID in a Tcl variable, then removes that force object:

set f10 [ add_force reset 1 300 ]
remove_forces $f10

The following example removes all force objects from the current simulation:

remove_forces -all