Versal Adaptive SoC Power Domains - 2023.2 English

Power Design Manager User Guide (UG1556)

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2023.2 English

In the AMD Versal™ adaptive SoC architecture, different functional blocks are partitioned into power domains that are powered using dedicated supply rails. These supply rails can be connected to different power sources. The following figure shows how the circuitry on a Versal device is partitioned into power domains, as it appears at the device level.

Note: Exact layout can vary based on the targeted Versal device and its size.
Figure 1. Device Level Power Domains
Table 1. Power Domain Descriptions
Power Device Rail Description
PMC Device Rail (VCC_PMC) This is an always-on device rail for the device. The only core domain that should be up for the device operation to start and stay maintained.
PS Low-Power Device Rail (VCC_PSLP) This device rail must be up in addition to the PMC device rail for the primary device configuration through USB to get started. This device rail supplies power to RPUs (Realtime Processing Unit - Arm® Cortex-R5F core). This device rail is associated with many of the low-power modes,therefore, it includes power islands to satisfy the power requirements of these modes.
PS Full-Power Device Rail (VCC_PSFP) This device rail supplies power to APUs (Application Processing Unit - Arm® Cortex®-A72 core) within the processing systems (PS) that are not required during low-power modes.
NoC and DDRMC Device Rail (VCC_SOC) This power device rail includes the NoC and Hardened Memory Controller. This device rail should be up when the PL device rail is up.
Core and PL Device Rail (VCCINT) This device rail includes the internal core logic of the PL, CCIX PCIe® Module (CPM), and AI Engine.
PL RAM Device Rail (VCC_RAM) This supply provides the power to the PL RAMs and the PL clocking network. This rail is expected to be up always while the VCCINT device rail is up. If this supply is down, VCCINT device rail incurs a power-on reset.
Battery-Powered Device (BPD) Rail (VCC_BATT) This is the power device rail for the RTC Core and the battery-backed RAM (BBRAM). This device rail is on the battery supply (VCC_BATT) if the device is off; else, the PMC/PS Auxiliary supply (VCCAUX_PMC) provides the power to this device rail.
Analog Device Rail This device rail has three supplies, namely GT*_AVCC, GT*_AVTT, and GT*_VCCAUX. GT*_AVCC is the analog supply for internal analog circuits of the transceivers. This includes analog circuits for the PLL, transmitters, and receivers. GT*_AVTT is the analog supply for transmitter and receiver termination circuits. GTY_VCCAUX is the auxiliary analog QPLL voltage supply for the transceivers.
Note: For GTP, the rails are GTP_AVCC, GTP_AVTT, and GTP_VCCAUX. For GTM, the rails are MGTM_AVCC, MGTM_AVTT, and MGTM_VCCAUX. Depending on the device, this can be GTY, GTYP and GTM transceivers.
VCCO Device Rail This device rail includes all the VCCO supplies. It powers all device I/Os.