UltraScale+ Power Domains - 2023.2 English - UG1556

• All CLB resources
• All routing resources
• Entire clock tree, including all clock buffers
• Block RAM/FIFO
• DSP slices
• All input buffers
• Logic elements in the IOB (ILOGIC/OLOGIC)
• Tri-Mode Ethernet MAC
• Clock Managers (MMCM, PLL, DCM, etc.)
• PCIe and PCS portion of MGTs

• All output buffers
• Some input buffers
• Input termination
• Reference resistors to DCI

V_CCAUX

^VCCAUX_IO

• Clock Managers (MMCM, PLL, DCM, etc.)(1)
• IODELAY/IDELAYCTRL
• All output buffers
• Differential Input buffers
• V_REF-based, single-ended I/O standards, for example, HSTL18_I

M_GTAVCC

M_GTAVTT

M_GTVCCAUX

V_{CCINT_GT}

• Analog supply voltages for PMA circuits of transceivers
• Transceiver termination circuits
• Quad PLL
• GTM Core supply

V_{CC_PSINTFP}

V_{CC_PSINTLP}

V_{CC_PSAUX}

V_{CCPSINTFP_DDR}

V_{CC_PSPLL}

V_{PS_MGTRAVCC}

V_{PS_MGTRAVTT}

V_{CCO_PSDDR}

V_{CCO_PSDDR_PLL}

V_{CCO_PSIO}

V_{CCINT_VCU}

• Zynq UltraScale+ MPSoC ⁽²⁾:
  • Processor
  • Memory
  • I/O
  • Peripherals

• Input buffers in HPIO bank
• Output buffers in HPIO bank
• ISERDES/OSERDES
• IDDR, ODDR
• IFF, OFF
• IDELAY, ODELAY
• BITSLICE - all components
• HBM
  • HBM AXI Switch
  • HBM MC
  • PHY
  • Clock
  • IO (Read and Write)