HBM for UltraScale+ Devices - 2023.2 English

Power Design Manager User Guide (UG1556)

Document ID
UG1556
Release Date
2023-10-18
Version
2023.2 English

The HBM tab is available only for AMD Virtex™ UltraScale+™ HBM devices. This tab is used to estimate the power of high bandwidth memory. Each HBM device contains one or two 32 Gb memory stacks.

The Page Hit Rate is the estimated rate of a memory transaction to access an open page, which results in the fastest access. For example, sequential memory accesses are more likely to occur within an open page that reduces power and increases efficiency.

In the main table, each row represents a pseudo-channel associated with an AXI port capable of accessing a contiguous 2 Gb section of an HBM stack. There are 16 pseudo-channels associated with Stack0 and 16 associated with Stack1. Each of the 16 psuedo-channels must access the HBM using one of the eight dedicated memory controllers and each memory controller simultaneously accesses two HBM 2 Gb sections.

Data Rate for each memory controller is specified in Mbps. The valid range is from 100 to 1800 (1600 for -1 device speed). There can be different rates within the same stack. However, they must be integer multiples (if the rates are different). For example, if a stack has a memory controller with a rate of 1800, the next slower valid rate is 900 (1/2) and the next slower rate after that is 450 (1/4) and so on.

The valid condition for Read and Write rates are as follows:

  • If the Page Hit Rate is less than 75%, the (Read Rate + Write Rate) is less than or equal to 50%
  • If the Page Hit Rate is greater than or equal to 75%, the (Read Rate + Write Rate) is less than or equal to 90%