DSP for UltraScale+ Devices - 2023.2 English

Power Design Manager User Guide (UG1556)

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2023.2 English

AMD device families have different Digital Signal Processing (DSP) blocks with different capabilities. To enter information for DSP first review the UltraScale Architecture DSP Slice User Guide (UG579) to understand the parameters in the DSP tab.

  • The default DSP configuration is assumed to be 27x18 in PDM. The toggle rate must be scaled accordingly for accurate power estimation. For example, if 18x18 DSP is expected to toggle 25%, then scale it by 0.86, which is 21.5% and enter into PDM. Similarly, scale the actual toggle rate by 0.8 for 12x12 configuration.
  • DSP slices have clock enable (CE) ports. When entering data in the Toggle Rate column remember to multiply your data input toggle rate with the DSP slice clock enable rate. For example, if random data (typically ~38% data toggle rate) is input into the DSP slice and the slice is clock enabled only 50% of the time, then the output data toggle rate should be scaled by the CE rate such that the data toggle rate becomes 19% (38% x 50%).
  • For families that have a register within the multiplier (MREG), using this pipeline register helps lower dynamic power.