Reserved Memory - 2023.2 English

Vitis Unified Software Platform Documentation: Embedded Software Development (UG1400)

Document ID
Release Date
2023.2 English

Reserved memory has been defined by the hardware and software programming environment for privileged use. This is typically true for memory containing interrupt vector locations and operating system level routines. The following table lists the reserved memory locations for MicroBlaze and Arm processors as defined by the processor hardware. For more information on these memory locations, refer to the corresponding processor reference manuals.

For information about the Arm Cortex A9 memory map, refer to the . For the Cortex-R5F, Cortex-A53, and Cortex-A72 memory map, refer to the Zynq UltraScale+ Device Technical Reference Manual (UG1085).

Note: In addition to these memories that are reserved for hardware use, your software environment can reserve other memories. Refer to the manual of the particular software platform that you are using to find out if any memory locations are deemed reserved.
Table 1. Hardware Reserved Memory Locations
Processor Family Reserved Memories Reserved Purpose Default Text Start Address
MicroBlaze 0x0 - 0x4F Reset, Interrupt, Exception, and other reserved vector locations. 0x50