pragma HLS latency - 2023.2 English

Vitis High-Level Synthesis User Guide (UG1399)

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2023.2 English


Specifies a minimum or maximum latency value, or both, for the completion of functions, loops, and regions.

Number of clock cycles required to produce an output.
Function latency
Number of clock cycles required for the function to compute all output values, and return.
Loop latency
Number of cycles to execute all iterations of the loop.

Vitis HLS always tries to minimize latency in the design. When the LATENCY pragma is specified, the tool behavior is as follows:

  • Latency is greater than the minimum, or less than the maximum: The constraint is satisfied. No further optimizations are performed.
  • Latency is less than the minimum: If the HLS tool can achieve less than the minimum specified latency, it extends the latency to the specified value, potentially enabling increased sharing.
  • Latency is greater than the maximum: If the HLS tool cannot schedule within the maximum limit, it increases effort to achieve the specified constraint. If it still fails to meet the maximum latency, it issues a warning, and produces a design with the smallest achievable latency in excess of the maximum.
Tip: You can also use the LATENCY pragma to limit the efforts of the tool to find an optimum solution. Specifying latency constraints for scopes within the code: loops, functions, or regions, reduces the possible solutions within that scope and can improve tool runtime. Refer to Improving Synthesis Runtime and Capacity for more information.

If the intention is to limit the total latency of all loop iterations, the latency directive should be applied to a region that encompasses the entire loop, as in this example:

Region_All_Loop_A: {
#pragma HLS latency max=10
Loop_A: for (i=0; i<N; i++) 
  ..Loop Body... 

In this case, even if the loop is unrolled, the latency directive sets a maximum limit on all loop operations.

If Vitis HLS cannot meet a maximum latency constraint it relaxes the latency constraint and tries to achieve the best possible result.

If a minimum latency constraint is set and Vitis HLS can produce a design with a lower latency than the minimum required it inserts dummy clock cycles to meet the minimum latency.


Place the pragma within the boundary of a function, loop, or region of code where the latency must be managed.

#pragma HLS latency min=<int> max=<int>


Optionally specifies the minimum latency for the function, loop, or region of code.
Optionally specifies the maximum latency for the function, loop, or region of code.
Note: Although both min and max are described as optional, at least one must be specified.

Example 1

Function foo is specified to have a minimum latency of 4 and a maximum latency of 8.

int foo(char x, char a, char b, char c) {
  #pragma HLS latency min=4 max=8
  char y;
  y = x*a+b+c;
  return y

Example 2

In the following example, loop_1 is specified to have a maximum latency of 12. Place the pragma in the loop body as shown.

void foo (num_samples, ...) {
  int i;
  loop_1: for(i=0;i< num_samples;i++) { 
  #pragma HLS latency max=12
    result = a + b;

Example 3

The following example creates a code region and groups signals that need to change in the same clock cycle by specifying zero latency.

// create a region { } with a latency = 0
  #pragma HLS LATENCY max=0 min=0
  *data = 0xFF;
  *data_vld = 1;