add_files - 2023.2 English

Vitis High-Level Synthesis User Guide (UG1399)

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2023.2 English


Adds design source files to the current project.

The tool searches the current directory for any header files included in the design source. To use header files stored in other directories, use the -cflags option to include those directories to the search path.


add_files [OPTIONS] <src_files>
  • <src_files> lists one or more supported source files.


-blackbox <file_name.json>
Specify the JSON file to be used for RTL blackbox. The information in this file is used by the HLS compiler during synthesizing and running C/C++ and co-simulation.
-cflags <string>
A string with any GCC compilation options.
-csimflags <string>
A string with any desired simulation compilation options. Flags specified with this option are only applied to simulation compilation, which includes C/C++ simulation and RTL co-simulation, not synthesis compilation. This option does not impact the -cflags option.
Specifies any files used as part of the design test bench. These files are not synthesized. They are used when simulation is run by the csim_design or cosim_design commands.

Do not use the -tb option when adding source files for the design. Use separate add_files commands to add design files and simulation files.


Add three design files to the project.

add_files a.cpp
add_files b.cpp
add_files c.cpp

Add multiple files with a single command line.

add_files "a.cpp b.cpp c.cpp"

Use the-tb option to add test bench files to the project. This example adds multiple files with a single command, including:

  • The test bench a_test.cpp
  • All data files read by the test bench:
    • input_stimuli.dat
      add_files -tb "a_test.cpp input_stimuli.dat"

    If the test bench data files in the previous example are stored in a separate directory (for example test_data), the directory can be added to the project in place of the individual data files.

    add_files -tb a_test.cpp
    add_files -tb test_data