Timeline Trace Viewer - 2023.2 English

Vitis High-Level Synthesis User Guide (UG1399)

Document ID
Release Date
2023.2 English

The Timeline Trace report is available after C/RTL Co-Simulation. The Timeline Trace viewer displays the runtime profile of the functions of your design. It is especially useful to see the behavior of dataflow regions after Co-simulation, as there is no need to launch the Vivado logic simulator to view the timeline.

Figure 1. Timeline Trace Viewer

Timeline Trace viewer displays multiple iterations through the various sub-functions of a dataflow region as shown in the preceding figure. It shows where the functions are starting and ending, and displays the Co-simulation data in tables below the timeline. To generate the Timeline Trace during C/RTL Co-simulatio you should enable cosim.trace_level=all and cosim.enable_dataflow_profiling=true options in the config file, or from the Config File Editor.

The Timeline Trace view also shows FIFO and PIPO channel stall/starve states with Full and Empty markers as shown above. In the preceding figure, you can see the read_data PIPO is empty, resulting in stalls 68% of the time as reported in the table below the graph.

The Dataflow Viewer displays a menu bar at the top of the report that includes the following features:

  • Zoom In/Zoom Out/Zoom Fit/Zoom Full commands
  • Toggle Table command to show or hide the table beneath the graph
  • Expand All/Collapse All to expand or collapse the design hierarchy
  • Previous Marker/Next Marker lets you move from one marker to the next in the timeline
  • Delete All Markers remove markers from the timeline
  • Legend command for the display