Schedule Viewer - 2023.2 English

Vitis High-Level Synthesis User Guide (UG1399)

Document ID
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2023.2 English

The Schedule Viewer provides a detailed view of the synthesized RTL, showing each operation and control step of the function, and the clock cycle that it executes in. It helps you to identify any loop dependencies that are preventing parallelism, timing violations, and data dependencies.

Figure 1. Schedule Viewer
  • The left vertical axis shows the names of operations and loops that will get implemented as logic in the RTL hierarchy. Operations are in topological order indicating that an operation on one line can only be driven by operations from a previous line, and will only drive an operation in a later line. Depending upon the type of violations found the Schedule Viewer shows additional information for each operation
    Tip: Each operation is associated with lines of source code. Right-click the operation to use the Goto Source command to open the input source code associated with the operation.
  • The top horizontal axis shows the clock cycles in consecutive order.
  • The vertical dashed line in each clock cycle shows the reserved portion of the clock period due to clock uncertainty. This time is left by the tool for the Vivado back-end processes, like place and route.
  • Each operation is shown as a gray box in the table. The box is horizontally sized according to the delay of the operation as percentage of the total clock cycle. In case of function calls, the provided cycle information is equivalent to the operation latency. Multi-cycle operations are shown as gray boxes with a horizontal line through the center of the box.
  • The Schedule Viewer also displays general operator data dependencies as solid blue lines. As shown in the preceding figure, when selecting an operation you can see solid blue arrows highlighting the specific operator dependencies. This gives you the ability to perform detailed analysis of data dependencies. A green dotted line indicates an inter-iteration data dependency. Memory dependencies are displayed using golden lines.
    Tip: By default all dependencies (blue lines) are shown between each operation in the critical timing path.
  • On the far right the HLS Module Hierachy is displayed alongside the Schedule Viewer to let you quickly navigate through the hierarchy of the design.

In the following figure the loop called COL_DCT_LOOP_DCT_OUTER_LOOP is selected. This is a pipelined loop and the initiation interval (II) is explicitly stated in the loop bar. Any pipelined loop is visualized unfolded, meaning one full iteration is shown in the schedule viewer. Overlap, as defined by II, is marked by a thick clock boundary on the loop marker. The total latency of a single iteration is equivalent to the number of cycles covered by the loop marker. In this case, it is six clock cycles.

Figure 2. Pipelined Loop

The Schedule Viewer displays a menu bar at the top of the report that includes the following features:

  • Zoom In/Zoom Out/Zoom Fit commands
  • A text field to enter search terms for specific operations or steps, and arrow commands (Previous Match or Next Match) to scroll up or down through the list of objects that match your search text
  • Legend command for the display.
Figure 3. Timing Violations

You can quickly locate timing violations and II violations using the toolbar menu in the in the Module Hierarchy view as shown in the preceding figure. To locate the operations causing the violation in the source code, right-click the operation and use the Goto Source command. A timing violation is a path of operations requiring more time than the available clock cycle. To visualize this, the problematic operation is represented in the Schedule Viewer in a red box.

Properties View

At the bottom of the Schedule Viewer, as shown in the top figure, is the Properties view that displays the properties of a currently selected object in the Schedule Viewer. This lets you see details of the specific function, loop, or operation that is selected in the Schedule Viewer. The types of elements that can be selected, and the properties displayed include:

  • Functions or Loops
    Initiation Interval (II)
    The number of clock cycles before the function or loop can accept new input data.
    Loop Iteration Latency
    The number of clock cycles it takes to complete one iteration of the loop.
    The number of clock cycles (and time) required for the function to compute all output values, or for the loop to complete all iterations.
    Name of function or loop.
    Indicates that the function or loop are pipelined in the RTL design.
    The timing slack for the function or loop.
    The number of iterations a loop completes.
    Resource Utilization
    Displays the number of BRAM, DSP, LUT, or FF used to implement the function or loop.
  • Operation and Storage Mapping
    Bitwidth of the Operation.
    Defines the implementation used for the specified operation or storage.
    Name of operation.
    Op Latency
    Displays the default or specified latency for the binding of the operation or storage.
    Operation which has been scheduled, for example, add, sub, and mult. For more information, refer to the BIND_OP or BIND_STORAGE pragmas or directives.
    Schedule Delay
    Specifies the delay associated with the operation.